Microfiche Appendix: There are 2 microfiche in total, and 103 frames in total.
The present invention relates to computer architectures, and in particular to architectures dedicated to the creation of graphical images to be printed or displayed.
The general concept of hardware acceleration of intensive computations such as graphical computations is known.
Recently, the number of gates able to be placed on an Application Specific Integrated Circuit (ASIC) has been increasing at a dramatic rate. As a result of these developments, it has become relatively common to implement a xe2x80x9csystem on a chipxe2x80x9d having a high degree of functionality in a single package. Unfortunately, increasing system complexity has brought with it correspondingly more difficult implementation, leading in turn to an increased likelihood of implementation errors. Often, the implementation errors are of a sufficiently catastrophic nature as to require re-engineering of the ASIC, which is inefficient in terms of time and costs.
Also, because ASIC chips are designed to perform a specific task, they can be relatively inflexible when it comes to other tasks. This is the case even when the other task is very closely related to, and may even be a modification of, the original task for which the ASIC was designed. The problem is exacerbated in the case of graphics ASICs, which have to deal with graphics formats and processes which change relatively frequently.
It is an object of the present invention to overcome or at least ameliorate one or more of the disadvantages of the prior art.
Accordingly, the invention provides a graphics processor comprising:
a plurality of interrelated functional modules;
at least one register associated with each of the functional modules, each register being configured to control the function of its associated functional module; and
an instruction controller for decoding instructions for use with the graphics processor, said instruction controller including register setting means to set the registers in accordance with a decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction.
Preferably, at least some of the registers include a semaphore access mechanism accessible by external modules, including the functional modules.
Desirably, wherein at least some of the functional registers include a status register, the contents of each of which is updateable by its associated register during or following execution of an instruction.
Preferably, each one of the functional modules provides a signal indicative of whether it is actively processing data.
In a preferred form, the register setting means is one of a plurality of units able to set register values, the graphics processor further including arbitrator means to control which of the units is able to set the register values at a given time.
In the following detailed description, the reader""s attention is directed, in particular, to FIG. 2 and any one or more of FIGS. 17 to 21, and their associated description, without intending to detract from the disclosure of the remainder of the description.
1.0 Brief Description of the Drawings
2.0 List of Tables
3.0 Description of the Preferred and Other Embodiments
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
3.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data Types and Data Manipulation
3.16 Data Normalization Circuit
3.17 Image Processing Operations of Accelator Card
3.17.1 Compositing
3.17.2 Color Space Conversion Instructions
a. Single Output General Color Space (SOGCS) Conversion Mode
b. Multiple Output General Color Space Mode
3.17.3 JPEG Coding/Decoding
a. Encoding
b. Decoding
3.17.4 Table Indexing
3.17.5 Data Coding Instructions
3.17.6 A Fast DCT Apparatus
3.17.7 Huffman Decoder
3.17.8 Image Transformation Instructions
3.17.9 Convolution Instructions
3.17.10 Matrix Multiplication
3.17.11 Halftoning
3.17.12 Hierarchial Image Format Decompression
3.17.13 Memory Copy Instructions
a. General purpose data movement instructions
b. Local DMA instructions
3.17.14 Flow Control Instructions
3.18 Modules of the Accelerator Card
3.18.1 Pixel Organizer
3.18.2 MUV Buffer
3.18.3 Result Organizer
3.18.4 Operand Organizers B and C
3.18.5 Main Data Path Unit
3.18.6 Data Cache Controller and Cache
a. Normal Cache Mode
b. The Single Output General Color Space Conversion Mode
c. Multiple Output General Color Space Conversion Mode
d. JPEG Encoding Mode
e. Slow JPEG Decoding Mode
f. Matrix Multiplication Mode
g. Disabled Mode
h. Invalidate Mode
3.18.7 Input Interface Switch
3.18.8 Local Memory Controller
3.18.9 Miscellaneous Module
3.18.10 External Interface Controller
3.18.11 Peripheral Interface Controller
APPENDIX Axe2x80x94Microprogramming
APPENDIX Bxe2x80x94Register tables